Renesas Electronics /R7FA6T2BD /SPI_B0 /SPSR

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Interpret as SPSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (000)SPCP0 (000)SPECM0 (0)SPDRF 0 (0)OVRF 0 (0)IDLNF 0 (0)MODF 0 (0)PERF 0 (0)UDRF 0 (0)SPTEF 0 (0)CENDF 0 (0)SPRF

SPDRF=0, SPTEF=0, MODF=0, CENDF=0, PERF=0, SPECM=000, SPCP=000, SPRF=0, OVRF=0, UDRF=0, IDLNF=0

Description

SPI Status Register

Fields

SPCP

SPI Command Pointer

0 (000): SPCMD0

1 (001): SPCMD1

2 (010): SPCMD2

3 (011): SPCMD3

4 (100): SPCMD4

5 (101): SPCMD5

6 (110): SPCMD6

7 (111): SPCMD7

SPECM

SPI Error Command

0 (000): SPCMD0

1 (001): SPCMD1

2 (010): SPCMD2

3 (011): SPCMD3

4 (100): SPCMD4

5 (101): SPCMD5

6 (110): SPCMD6

7 (111): SPCMD7

SPDRF

SPI Receive Data Ready Flag

0 (0): Receive data ready not detected

1 (1): Receive data ready detected

OVRF

Overrun Error Flag

0 (0): No overrun error is present.

1 (1): An overrun error is present.

IDLNF

SPI Idle Flag

0 (0): The SPI is in the idle state.

1 (1): The SPI is in the transfer state.

MODF

Mode Fault Error Flag

0 (0): Neither mode fault error nor underrun error is present.

1 (1): A mode fault error or underrun error is present.

PERF

Parity Error Flag

0 (0): No parity error is present.

1 (1): A parity error is present.

UDRF

Underrun Error Flag

0 (0): When MODF=0, neither mode fault error nor underrun error is present. When MODF=1, a mode fault error is present.

1 (1): When MODF=0, neither mode fault error nor underrun error is present. When MODF=1, an underrun error is present.

SPTEF

SPI Transmit Buffer Empty Flag

0 (0): The number of empty stages in the transmit FIFO ≤ the value set in SPDCR2.TTRG

1 (1): The number of empty stages in the transmit FIFO > the value set in SPDCR2.TTRG

CENDF

Communication End Flag

0 (0): The SPI is not communicating or communicating.

1 (1): The SPI communication completed.

SPRF

SPI Receive Buffer Full Flag

0 (0): The number of data stored in the receive FIFO ≤ number of frames set by the SPDCR2.RTRG bit.

1 (1): The number of data stored in the receive FIFO > number of frames set by the SPDCR2.RTRG bit.

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